As a method of increasing the capacity of and reducing the cost of a semiconductor memory device, there is a batch processing type stacked memory. The batch processing type stacked memory is manufactured as follows: a stacked body is formed by alternately stacking an insulating film and an electrode film on a semiconductor substrate, thereafter a through hole is formed in the stacked body by lithography, a block layer, a charge storage layer and a tunnel layer are deposited within the through hole in this order and a silicon pillar is embedded into the through hole.
In the stacked memory as described above, a memory transistor is formed at the intersection portion of the electrode film and the silicon pillar, and this serves as a memory cell. A selection gate electrode is provided on the stacked body, the silicon pillar is made to penetrate the selection gate electrode, the upper end of the silicon pillar is connected to a wiring in an upper layer and thus a selection transistor is formed between the selection gate electrode and the silicon pillar. Then, the selection transistor is controlled, and thus it is possible to switch whether or not the silicon pillar is connected to the wiring in the upper layer.